TMS320VC5409APGE12

Product Summary

The TMS320VC5409APGE12 is a fixed-point, digital signal processor. It is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This TMS320VC5409APGE12 provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The TMS320VC5409APGE12 also includes the control mechanisms to manage interrupts, repeated operations, and function calls.

Parametrics

TMS320VC5409APGE12 absolute maximum ratings: (1)Supply voltage I/O range:-0.3V to 4.0V; (2)Supply voltage core range:-0.3V to 2.0V; (3)Input voltage range:-0.3V to 4.5V; (4)Output voltage range:-0.3V to 4.5V; (5)Operating case temperature range:-40℃ to 100℃; (6)Storage temperature range:-55℃ to 150℃.

Features

TMS320VC5409APGE12 features: (1)Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus; (2)40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators; (3)17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation; (4)Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator; (5)Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle; (6)Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs); (7)Data Bus With a Bus Holder Feature; (8)Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space; (9)16K × 16-Bit On-Chip ROM Configured for Program Memory; (10)Enhanced External Parallel Interface (XIO2); (11)Single-Instruction-Repeat and Block-Repeat Operations for Program Code; (12)Block-Memory-Move Instructions for Better Program and Data Management; (13)Instructions With a 32-Bit Long Word Operand; (14)Instructions With Two- or Three-Operand Reads; (15)Arithmetic Instructions With Parallel Store and Parallel Load; (16)Conditional Store Instructions.

Diagrams