(Hong Kong)
Product Summary
The HY5DU281622ET-5 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which require high densities and high bandwidth. The HY5DU281622FTP-5 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
Parametrics
HY5DU281622ET-5 absolute maxing ratings: (1)Ambient Temperature TA: 0 ~ 70℃; (2)Storage Temperature TSTG: -55 ~ 125℃; (3)Voltage on Any Pin relative to VSS VIN, VOUT: -0.5 ~ 3.6V; (4)Voltage on VDD relative to VSS VDD: -0.5 ~ 3.6V; (5)Voltage on VDDQ relative to VSS VDDQ: -0.5 ~ 3.6V; (6)Output Short Circuit Current IOS: 50mA; (7)Power Dissipation PD: 2W; (8)Soldering Temperature Time TSOLDER: 260.10℃.sec.
Features
HY5DU281622ET-5 features: (1)2.8V +/- 0.1V VDD and VDDQ power supply supports 400/375/350/333/300MHz; (2)2.5V +/- 5% VDD and VDDQ power supply supports 275/250/200/166MHz; (3)All inputs and outputs are compatible with SSTL_2 interface; (4)JEDEC Standard 400 mil x 875 mil 66 Pin TSOP II, with 0.65mm pin pitch; (5)Fully differential clock inputs (CK, /CK) operation; (6)Double data rate interface; (7)Source synchronous - data transaction aligned to bidirectional data strobe (UDQS,LDQS); (8)Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ); (9)Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe.
Diagrams
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