XC3S1600E-5FG400C

Product Summary

The XC3S1600E-5FG400C Field-Programmable Gate Array (FPGA) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The XC3S1600E-5FG400C offers densities ranging from 100,000 to 1.6 million system gates. The XC3S1600E-5FG400C builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration.

Parametrics

XC3S1600E-5FG400C absolute maximum ratings: (1)Internal supply voltage: –0.5 to 1.32 V; (2)Auxiliary supply voltage: –0.5 to 3.00 V; (3)Output driver supply voltage: –0.5 to 3.75 V; (4)Input reference voltage: –0.5 to VCCO+0.5 V; (5)Voltage applied to all User I/O pins and Dual-Purpose pins: –0.5 to VCCO+0.5 V, Voltage applied to all Dedicated pins: –0.5 to VCCAUX+0.5 V; (6)Electrostatic Discharge Voltage Human body model: –2000 to +2000 V; (7)Charged device model: –500 to +500 V; (8)Machine model: –200 to +200 V; (9)Junction temperature: 125 ℃; (10)Storage temperature: –65 to 150 ℃.

Features

XC3S1600E-5FG400C features: (1)Very low cost, high-performance logic solution for high-volume, consumer-oriented applications; (2)Proven advanced 90-nanometer process technology; (3)Multi-voltage, multi-standard SelectIO?interface pins: Up to 376 I/O pins or 156 differential signal pairs, LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards, True LVDS, RSDS, mini-LVDS differential I/O, 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling, Enhanced Double Data Rate (DDR) support; (4)Abundant, flexible logic resources: Densities up to 33,192 logic cells, including optional shift register or distributed RAM support, Efficient wide multiplexers, wide logic, Fast look-ahead carry logic, Enhanced 18 x 18 multipliers with optional pipeline, IEEE 1149.1/1532 JTAG programming/debug port; (5)Hierarchical SelectRAM?memory architecture: Up to 648 Kbits of fast block RAM.

Diagrams