(Hong Kong)
Product Summary
The XC4003E-1PQ100C Field Programmable Gate Array (FPGA) is implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). The XC4003E-1PQ100C has generous routing resources to accommodate the most complex interconnect patterns. It is customized by loading configuration data into internal memory cells. The XC4003E-1PQ100C can either actively read its configuration data from an external serial or byte-parallel PROM (master modes), or the configuration data can be written into the FPGA from an external device (slave and peripheral modes).
Features
XC4003E-1PQ100C features: (1)Highest Performance-3.3 V XC4000XL; (2)Highest Capacity-Over 180,000 Usable Gates; (3)5 V tolerant I/Os on XC4000XL; (4)0.35 mm SRAM process for XC4000XL; (5)Additional Routing Over XC4000E: almost twice the routing capacity for high-density designs; (6)Buffered Interconnect for Maximum Speed Blocks; (7)Improved VersaRing I/O Interconnect for Better Fixed Pinout Flexibility; (8)12 mA Sink Current Per XC4000X Output; (9)Flexible New High-Speed Clock Network: Eight additional Early Buffers for shorter clock delays, Virtually unlimited number of clock signals.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||
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 XC4003E-1PQ100C |
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IC FPGA C-TEMP 5V 1-SPD 100-PQFP |
Data Sheet |
Negotiable |
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| Image | Part No | Mfg | Description | |
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XC4000 |
Other |
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Data Sheet |
Negotiable |
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XC4000A |
Other |
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Data Sheet |
Negotiable |
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XC4000E |
Other |
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Data Sheet |
Negotiable |
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XC4000H |
Other |
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Data Sheet |
Negotiable |
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XC4000X |
Other |
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Data Sheet |
Negotiable |
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XC4000XL |
Other |
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Data Sheet |
Negotiable |
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